1. Field of the Invention
The present invention relates to semiconductor integrated circuits and in particular to a semiconductor integrated circuit with improved coupling wiring between IO buffers and bonding pads.
2. Description of Related Art
In recent semiconductor integrated circuits, the number of elements has been significantly increased with increase in or complication of equipped functions. This also significantly increases the number of input/output signals of each semiconductor integrated circuit required for implementing these functions. To make it possible to input/output a larger number of input/output signals to/from a semiconductor integrated circuit, it is necessary to set a large number of bonding pads (coupling pads). For this reason, such techniques as reduction of the pad size of bonding pads and single row arrangement of pads have been reviewed aiming at such techniques as multi-row arrangement typified by staggered arrangement.
For example, Japanese Unexamined Patent Publication No. 2007-305822 (FIG. 1) discloses a semiconductor integrated circuit in which the following measure is taken: a row of coupling pads 141a to 141c and a row of coupling pads 142a to 142d are set over IO cells 131a to 131g (IO buffers) in an IO area 30 so that they are displaced from each other; coupling pads 143a to 143d are set over a core power supply wiring 121 along one side of the core area 120; the respective pad pitches P of the coupling pads 141a to 141c, 142a to 142d, and 143a to 143d are so set that the relation of P=2S, where S is the cell pitch of the IO cells, holds; P/3 (=2S/3) is taken as the pad pitch of the entire coupling pads 141a to 141c, 142a to 142d, and 143a to 143d so that three coupling pads are set for two IO cells. (Refer to FIG. 9.) According to the patent document, this makes it possible to prevent shortage of coupling pads for power supply to a core area and obviate necessity for reducing the cell width of IO cells.
In recent years, the following practice has been used especially in ASIC (Application Specific Integrated Circuit) products and the like developed based on customer requested specifications: the arrangement of the terminals of each semiconductor integrated circuit is determined to a board substrate produced by a customer itself. However, the following takes place when electrical characteristic requirements as a requested specification are exact, when noise has large influence on adjacent wiring over a board substrate depending on the alignment sequence of terminals, or on the other like occasions: it becomes necessary at the final stage of designing to change wiring over a board substrate or its routing or rearrange the terminals of a semiconductor integrated circuit. To change the coupling of bonding pads in an existing semiconductor integrated circuit, it is inevitable to change wiring for coupling with IO buffers or the arrangement of IO buffers (IO cells). Change to wiring for coupling with IO buffers inevitably involves change to the arrangement of IO buffers and their peripheral elements to ensure a wiring area. Change to the arrangement of IO buffers leads to change or addition of the arrangement of coupled circuit elements resulting from change to the arrangement of the IO buffers, replacement of arranged elements, and change of the routing of coupling wiring. Further, change of routing increases or decreases the delay of coupling wiring and this degrades electrical characteristics. This requires major changing work such as second review of the arrangement of elements or review of wiring and accompanying detailed verification of operation, arrangement, and the like. As a result, a significant reversion is inevitable in designing. The number of functions and elements equipped in each semiconductor integrated circuit will be continuously increased in the future and a larger number of bonding pads will be arranged. This will also increase the occurrences of rearrangement of terminals. Therefore, a method that facilitates rearrangement of terminals is demanded.
As a technique that makes it possible to rearrange terminals, for example, Japanese Unexamined Patent Publication No. 2007-305822 (FIG. 1) discloses a semiconductor integrated circuit in which the following measure is taken: lead-in wirings 211 to 216 for external terminals coupled to external terminals 201 to 206 and lead-in wirings 221 to 226 for internal circuits coupled to internal circuits are located in an identical wiring layer; and wiring line segments 241 to 243 for coupling lead-in wirings over two wiring layers sandwiching it are arranged so that the following is implemented: they are alternated between the upper layer and the lower layer and the two wiring layers intersect with the lead-in wirings for internal circuits and one of the two wiring layers intersects with the lead-in wirings for external terminals. The relation of coupling between the internal circuits and the external terminals is modified by changing the arrangement of contacts 231 to 234 coupling the wiring layers together. (Refer to FIG. 11.)